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    <description>Latest 20 threads of 《Cadence Allegro 16.6实战必备教程》</description>
    <copyright>Copyright(C) Cadence Allegro视频学习|电路知识笔记</copyright>
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    <item>
      <title>软件打不开文件</title>
      <link>http://www.pcbba.com/thread-21646-1-1.html</link>
      <description><![CDATA[这是什么原因？]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>1234563</author>
      <pubDate>Sun, 28 Jul 2019 09:11:48 +0000</pubDate>
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    <item>
      <title>关于作品展示区</title>
      <link>http://www.pcbba.com/thread-9584-1-1.html</link>
      <description><![CDATA[请问版主能放一些完成的PCB设计源文件给新手学习吗？]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>chen敏</author>
      <pubDate>Thu, 19 Oct 2017 07:45:55 +0000</pubDate>
    </item>
    <item>
      <title>cadence蛇形布线详细步骤</title>
      <link>http://www.pcbba.com/thread-9426-1-1.html</link>
      <description><![CDATA[最近在练习Cadence蛇形布线，发现这款软件不能直接对线进行蛇形走线，必须先用connect将线布好，然后才能用delay tune 进行蛇形走线，是不是我操作步骤错误？还是因为cadence的却是这样操作的？请求各位懂的解！]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>智勇双全</author>
      <pubDate>Wed, 19 Jul 2017 08:56:16 +0000</pubDate>
    </item>
    <item>
      <title>cadence16.6 原理图另存后没有下层图是什么原因，求解答？</title>
      <link>http://www.pcbba.com/thread-9379-1-1.html</link>
      <description><![CDATA[cadence16.6 原理图另存后没有下层图是什么原因，求解答？]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>yezi1266</author>
      <pubDate>Wed, 14 Jun 2017 03:22:35 +0000</pubDate>
    </item>
    <item>
      <title>ALLEGRO点击SETUP USERPREFRENCE窗口跳不出来</title>
      <link>http://www.pcbba.com/thread-9300-1-1.html</link>
      <description><![CDATA[求助，各位大神，我用16.6版本之前用的好好的，这两天突然发现点击SETUP USERPREFRENCE和PALCE-MANUALLY窗口跳不出来，有时候界面会变白闪一下。请问这是啥情况啊，重装了也不行]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>olyoxia</author>
      <pubDate>Fri, 17 Feb 2017 02:42:50 +0000</pubDate>
    </item>
    <item>
      <title>orcad16.6导出网表错误</title>
      <link>http://www.pcbba.com/thread-9283-1-1.html</link>
      <description><![CDATA[大显们，帮助看一下导出网表时出现是非法字符。怎么解决啊。不只这一个项目导出有非法字符，我所有项目导网表都提示有非法字符。 求大显发表你们的解决办法
Spawning... \&quot;C:\\Cadence\\SPB_16.6\\tools\\capture\\pstswp.exe\&quot; -pst -d \&quot;F:\\项目文件\\VR_V004_S900\\V004S3_S90 ...]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>as3218710</author>
      <pubDate>Fri, 30 Dec 2016 02:42:15 +0000</pubDate>
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    <item>
      <title>cadence下多个工程导出BOM</title>
      <link>http://www.pcbba.com/thread-9212-1-1.html</link>
      <description><![CDATA[各位，
        请问我有多个PCB板子，每个板子都有部分器件是重复的，如何导出BOM？谢谢大家！]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>瓜郎</author>
      <pubDate>Thu, 29 Sep 2016 09:18:17 +0000</pubDate>
    </item>
    <item>
      <title>请教，覆铜时元件中间的空白部分如何保留，谢谢</title>
      <link>http://www.pcbba.com/thread-9161-1-1.html</link>
      <description><![CDATA[覆铜时元件中间的空白部分如何保留，谢谢
因为元件很多，通过一个个挖空的方法，太麻烦了。请问下是否还有更方便的方法。]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>eddiej</author>
      <pubDate>Wed, 27 Jul 2016 09:10:24 +0000</pubDate>
    </item>
    <item>
      <title>cadence 16.6版本的show element功能无法选中走线坐标</title>
      <link>http://www.pcbba.com/thread-9134-1-1.html</link>
      <description><![CDATA[大家好！我现在用的cadence版本是16.6，当我在allegro中选中show element功能之后，find中选中cling，然后去点击一段cling，打开的show element对话框中点击cling走线的相应坐标只能定位而不能像低版本16.3 16.5一样相应选中对应坐标。请问cadence 16.6版本能否进行相应 ...]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>duanjianbo3330</author>
      <pubDate>Tue, 05 Jul 2016 05:09:25 +0000</pubDate>
    </item>
    <item>
      <title>等长设置教程</title>
      <link>http://www.pcbba.com/thread-9097-1-1.html</link>
      <description><![CDATA[请问下，等长设置这块的教程在那有？72讲视频里面看目录冒似没找着]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>yusong815</author>
      <pubDate>Fri, 10 Jun 2016 04:37:05 +0000</pubDate>
    </item>
    <item>
      <title>candence导入dxf</title>
      <link>http://www.pcbba.com/thread-7783-1-1.html</link>
      <description><![CDATA[DXF文件直接导入到candence 作为pCB的板框，可是边框不是一个整体，如何将边框弄成一个整理]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>lw_wwq</author>
      <pubDate>Wed, 11 May 2016 11:23:38 +0000</pubDate>
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    <item>
      <title>对class SUBclass了解的不是很深入</title>
      <link>http://www.pcbba.com/thread-4400-1-1.html</link>
      <description><![CDATA[论坛里关于这方面的知识很少]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
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      <pubDate>Mon, 25 Apr 2016 14:52:21 +0000</pubDate>
    </item>
    <item>
      <title>今天用ALLEGRO画原理图，然后打开界面发现不对，这界面是什么情况</title>
      <link>http://www.pcbba.com/thread-4385-1-1.html</link>
      <description><![CDATA[接下来上图]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>Xug</author>
      <pubDate>Sat, 16 Apr 2016 03:50:04 +0000</pubDate>
    </item>
    <item>
      <title>贴片元件的热风焊盘和隔离焊盘有必要设置吗</title>
      <link>http://www.pcbba.com/thread-4375-1-1.html</link>
      <description><![CDATA[RT，最近买了《Cadence Allegro16.6实战必备教程》自学Candence画板，不知道贴片元件封装的热风焊盘和隔离焊盘有必要设置吗，有的话就顺便画上了，要不然以后还得再次修改封装不够费劲的，请高手指点一下]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>1328616904</author>
      <pubDate>Mon, 11 Apr 2016 08:26:59 +0000</pubDate>
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    <item>
      <title>求解封装的一些知识</title>
      <link>http://www.pcbba.com/thread-2421-1-1.html</link>
      <description><![CDATA[请问大神们，元件的Assembly_Top 装配层，Place_Bound_TOP,    Silk Screen_Top层，是不是一定要按照元件的尺寸去画封装，可不可以不按照元件的标准去画，随便画了框就行。]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>xiaozhou123</author>
      <pubDate>Thu, 25 Feb 2016 01:19:50 +0000</pubDate>
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    <item>
      <title>《Cadence Allegro16.6实战必备教程》</title>
      <link>http://www.pcbba.com/thread-2188-1-1.html</link>
      <description><![CDATA[小哥这个视频教程链接进不去了，谁有给分享个呗]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>qiaomu</author>
      <pubDate>Mon, 04 Jan 2016 09:27:23 +0000</pubDate>
    </item>
    <item>
      <title>间距问题</title>
      <link>http://www.pcbba.com/thread-1398-1-1.html</link>
      <description><![CDATA[最近在焊盘上打埋孔的时候报错，麻烦大神帮忙解答下]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>aallon</author>
      <pubDate>Thu, 29 Oct 2015 09:07:41 +0000</pubDate>
    </item>
    <item>
      <title>关于公司的原理图库和封装库管理</title>
      <link>http://www.pcbba.com/thread-1299-1-1.html</link>
      <description><![CDATA[公司一直都是另一个同事画PCB，原理图库和封装库都在他的电脑上（小公司，不规范啊）。我想问下，怎么建立公司的共享的原理图和封装库啊。我记得Cadence可以生成一个配置文件，每个人加载配置文件就能共享，可我不会搞啊。我看小哥的书和其他同类书里面好像都没讲……]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>Russeler</author>
      <pubDate>Thu, 15 Oct 2015 08:06:41 +0000</pubDate>
    </item>
    <item>
      <title>软件使用时遇到的问题</title>
      <link>http://www.pcbba.com/thread-1201-1-1.html</link>
      <description><![CDATA[以前在另外一个公司安装的软件可以很少的使用，现在换了个公司，换了个电脑，软件使用上有些不一样，（都为默认设置），想像各位大神请教下。
1、打开软件时，每次都要选择具体的每一个，已经做了默认设置，但是没用，下次打开还是需要选择
2、软件打开后，最上面一栏 ...]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>aallon</author>
      <pubDate>Fri, 11 Sep 2015 07:17:23 +0000</pubDate>
    </item>
    <item>
      <title>有关差分等长问题！</title>
      <link>http://www.pcbba.com/thread-1195-1-1.html</link>
      <description><![CDATA[请教小哥一问题呀！镁光的x16 SDRAM 的数据控制线DQML和DQMH要做差分等长不呀！]]></description>
      <category>《Cadence Allegro 16.6实战必备教程》</category>
      <author>lxcxab</author>
      <pubDate>Mon, 07 Sep 2015 02:59:23 +0000</pubDate>
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