本帖最后由 龙凤呈祥 于 2015-9-9 07:57 编辑

The MostImportant EMC Design Guidelines
最重要的电磁兼容(EMC)设计指南


译于2015-9-3
   【题记】:感谢QQ昵称为湖北—木石子的朋友提供英文资料,我已翻译完毕并对译文进行了自校正,为方便大家中英双语对照并及时纠错,特将译文敲字到每一段英文原话下面。今发帖到论坛给大家分享,共同学习。因水平有限,敬请广大朋友们批评指正,谢谢。
    Here are fourimportant design guidelines that are often overlooked even though they can beamong the easiest to implement early in the design process.
这里有四个重要的设计准则,这些经常被忽视,即使他们可能在早期的设计过程中最容易实现。

      
Design Guideline#1: (General) Minimize the loop areas associated with high-frequency power andsignal currents.
设计原则1#(通常)尽量减小关联高频电源和信号电流的闭合回路的面积。
    This simplerule is on nearly everybody's list of EMC guidelines, but it often gets ignoredor compromised in favor of other guidelines. Often the board designer doesn'teven know where the signal currents flow. Digital circuit designers like tothink of signals in terms of their voltage. Signal integrity and EMC engineersmust think of signals in terms of their current.
    这个简单的规则几乎出现在每个人的电磁兼容(EMC)设计指南列表中,但它往往被忽视或者在有利于其他准则的时候被折中做出让步。经常出现的情况是,电路板设计师甚至不知道信号流经哪里。数字电路设计人员侧重考虑电压信号。信号完整性和电磁兼容工程师则必须考虑电流信号。

There are two things that every good circuit designer should know aboutsignal currents.
每一个优秀的电路设计者都应该知道关于信号电流的以下两个方面的常识:
1、Signal currents always return to their source (i.e.current paths are always loops)
1、 信号电流总是返回到它们的源头。(即电流路径总是形成闭合回路。)
2、Signal currents take the path(s) of leastimpedance.
2、信号电流经过的是最小阻抗的路径。
    At megahertz frequencies and higher,signal current paths are relatively easy to identify. This is because the pathof least impedance at high frequencies is generally the path of leastinductance, which is generally the path that minimizes the loop area. Currentsreturn as close as possible to the path of the outgoing current. At low frequencies(generally kHz frequencies and below), the path of least impedance tends to bethe path(s) of least resistance. Low frequency currents are more difficult totrace, since they will spread out. Significant current return paths may berelatively distant from the outgoing current path.
    在兆赫兹(MHz)频段甚至更高频率时,信号电流的路径是相对容易识别的。这是因为在高频时的最小阻抗的路径通常是电感最小的路径,这是最大限度地减少环路面积的一般路径。电流返回尽可能接近输出电流的路径。在低频段(一般为千赫兹(KHz)频段及以下),最小阻抗的路径往往是电阻最小的路径。低频电流更难以跟踪,因为它们会扩散。显著的电流回流路径可能是相对远离电流输出的路径。


Design Guideline #2: Don't Split, Gap orCut the Signal Return Plane.
设计原则2# :不要分裂、使出现缺口或者切断信号回流平面。
    Sure, there are some situations where awell-placed gap in the return plane might be called for. However, thesesituations are relatively rare and always involve a need to control the flow oflow-frequency currents. The safest rule-of-thumb is to provide one solid planefor returning all signal currents. In situations where you expect that aparticular low-frequency signal is susceptible or is capable of interferingwith the circuitry on your board, use a trace on a separate layer to returnthat current to its source. In general, never split, gap or cut your board'ssignal return plane. If you are convinced that a gap is necessary to prevent alow-frequency coupling problem, seek advice from an expert. Don't rely ondesign guidelines or application notes and don't try to implement a scheme that"worked" in someone else's "similar" design.
    当然,也有一些情况下,一个在回流平面上放置很好的缺口可能会被调用。不管怎样,这些情况是相对罕见的,而且总是涉及需要控制的低频电流的流动。最安全的经验法则是为返回所有的信号电流提供一个坚实的平面。在你期望的某个特定低频信号的情况下,或是能够干扰你的电路板,使用一个单独的层上的线路以返回电流到源头。一般来说,从来没有分裂、使出现缺口或者切断信号回流平面。如果你确信为防止出现低频耦合问题而一个使用缺口是必要的话,请咨询专家建议。不要依赖于设计指南或应用说明,也不要试图实施一个在别人眼里看起来类似的设计方案。


Design Guideline #3: Don't LocateHigh-Speed Circuitry between Connectors.
设计原则3#不要在连接器之间布置高速电路。

    Among board designs that we havereviewed or evaluated in our lab, this is one of the most common problems we'veencountered. Many times simple board designs that should have had no trouble atall meeting EMC requirements at no additional cost or effort, wind up beingheavily shielded and filtered because they violated this simple rule.
    在电路板设计过程中,我们已经在我们的实验室进行审查或评估,这是我们遇到的最常见的问题之一。很多时候,简单的板子设计应该没有问题,在所有符合电磁兼容要求的情况下,没有额外的成本,风的影响因素也被过滤掉了,因为他们违反了这个简单的规则。

    Why is the location of connectors soimportant? At frequencies below a few hundred megahertz, wavelengths are on theorder of a meter or longer. Any possible antennas on the printed circuit boarditself tend to be electrically small and therefore inefficient. However, cablesor other devices connected to a board can serve as relatively efficientantennas.
    为什么连接器的位置如此重要呢?在低于几百MHz频率时,波长在一米及以上。印刷电路板上任何可能的天线往往是电小天线,因此效率低下。然而,连接到一个电路板的电缆或其他设备可以作为相对有效的天线。

    Signal currents flowing on traces andreturning through solid planes result in small voltage differences between anytwo points on the plane. These voltage differences are generally proportionalto the current flowing in the plane. When all connectors are placed along oneedge of a board, the voltage between them tends to be negligible. However,high-speed circuitry located between connectors can easily develop potentialdifferences of a few millivolts or greater between the connectors. Thesevoltages can drive currents onto attached cables causing the product to exceedradiated emissions requirements.
    信号电流在导线中流动以及经过固体平面的回流结果是在平面上任意两点间存在一个小的电压差。这些电压通常是与流经平面的电流的大小成正比。所有的连接器被放在板的一个边缘时,它们之间的电压往往是可以忽略不计的。然而,布局在连接器之间的高速电路可以很容易的产生mV级或者更大的压差。这些电压可以驱动电流到连接电缆,导致产品超过辐射的排放要求。


Design Guideline #4: Control SignalTransition Times
设计原则4#控制信号的转换过渡时间。

    A board operating with a clock speed of100 MHz should never fail to meet a radiated emissions requirement at 2 GHz. Awell-formed digital signal will have a significant amount of power in the lowerharmonic frequencies, but not so much power in the upper harmonics. Power inthe upper harmonic frequencies is best controlled by slowing the transitiontimes in digital signals. While, excessively long transition times can causesignal integrity and thermal problems, an engineering compromise must bereached between these competing requirements. A transition time that isapproximately 20% of a bit period results in a reasonably good-lookingwaveform, while minimizing problems due to crosstalk and radiated emissions.Depending on the application, transitions times may need to be more or lessthan 20% of the bit period, however transitions times should not be left tochance.
    一个以100MHz时钟速度运行的电路板,应该永远不能满足2 GHz的辐射排放要求。一个良好的数字信号将有一个显著的功率量在较低的谐波频率,但没有这么多的功率在较高的谐波。在较高谐波频率时的功率,通过减缓在数字信号中的转换过渡时间的方法,可以得到很好地控制。同时,过长的转换过渡时间会导致信号的完整性和热问题,必须达到这些相互竞争的要求之间的工程上的妥协折中。一个过渡时期,约20%的比特周期的结果产生的是一个合理的好看的波形,同时最大限度地减少由于串扰和辐射产生的问题。根据不同的应用程序,转换时间可能需要或多或少于20%的比特周期,但是转换时间不应该留给机会。

There are threecommon methods for controlling rise and fall times in digital logic.
数字逻辑电路中控制上升和下降时间的三种常用方法如下:
1.     Use a logicfamily with a controlled slew-rate.
1、采用控制压摆率的逻辑器件系列。
2.     Put a resistoror a ferrite in series with a device's output.
2、在设备的输出端串联一个电阻或者铁氧体。
3、Put a capacitor in parallel with a device'soutput.
3、在设备的输出端并连一个电容。

    The first choice is often the easiestand most effective option. However, the use of a series resistor gives thedesigner more control and usually costs less. Capacitors can actually increasethe amount of high-frequency current drawn by the source device and in mostcases are not an appropriate choice.
    第一种方法往往是最简单和最有效的选择。然而,使用一个串联电阻,使设计者控制的更多而且通常这个方法成本更低。电容器实际上可以增加由源设备所引起的高频电流的量,在大多数情况下,这并不是一个恰当的选择。

    Note that it is never a good idea to tryto slow down or filter a single-ended signal by impeding the flow of current inthe return path. For example, one should never intentionally route a low-speedtrace over a gap in a return plane or put a ferrite on a ground in an attemptto filter out the high-frequency noise.
    请注意,从来没有一个好主意通过阻碍电流的回流路径试图减缓或过滤一个单端信号。例如,一个人不应该故意在信号回流平面经过一个缺口对低速线路布线或者在地平面放一个铁氧体来试图滤除高频噪声。
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