Cadence SPB16.6补丁网盘下载-042号补丁-电路知识笔记

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本帖最后由 lbmone 于 2015-2-7 18:44 编辑

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Cadence SPB16.6补丁-042号补丁网盘下载
更新详细内容如下：
DATE: 01-30-2015 HOTFIX VERSION: 042
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CCRID  PRODUCT       PRODUCTLEVEL2 TITLE
==========================================================
1334361  ALLEGRO_EDITOR                INTERACTIV       ZCopy should be able to copy multipleclines
1348389  CIS                         PART_MANAGER    Update selected part status should re-queryevery time the command is run
1349342  ALLEGRO_EDITOR       EDIT_ETCH       Need information on how to resolve(SPMHA1-170): No available buffer identifiers.
1349849  CIS                         OTHER             Capture crashes on generatingvariant reports
1349983  PSPICE                      SIMULATOR       Simulation aborts if save data optionis greater than 1 sec
1350477  PSPICE                      SIMULATOR       RPC server is unavailable
1353830  SIG_INTEGRITY       SIMULATION             xtalk analysis leads to crash
1354644  ALLEGRO_EDITOR       EXTRACT          Extracta does not extract a value forspecific property
1355337  ALLEGRO_EDITOR       EDIT_ETCH       Windows 8 Route Connect produces Buffererror.
1355522  SIP_LAYOUT          IC_IO_EDITING    Option to select reference point foralignment should be available when aligning single drivers
1355737  ALLEGRO_EDITOR       EDIT_ETCH       No available buffer identifiers causeloss of control in a routing phase
1356373  ALLEGRO_EDITOR       DRC_CONSTR       Design is crashing when attempting toupdate the DRCs.
1356684  SIP_LAYOUT          SYMB_EDIT_APPMOD Enhance highlight ofswappable pins excluding the pin to be swapped to
1358383  ALLEGRO_EDITOR       MODULES          mdd file is not created correctly
1358558  CONCEPT_HDL          GLOBALCHANGE    "Global Component Change" could not update parts.
1359780  ALLEGRO_EDITOR       EDIT_ETCH       The board database crashes on usingRoute Connect after some editing of traces.
1360416  SIP_LAYOUT          OTHER             SiP Design Variant not beingcreated on the design
1360630  FSP                         ALLEGRO_INTEGRAT For Fixed Internaland Fixed External nets, FSP shows net schedule difference in PCB Editor
1361157  ALLEGRO_EDITOR       GRAPHICS          3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on boardfile.
1361925  FSP                         DE-HDL_SCHEMATIC Port is notconnected for the nets having netname as NC.
1362865  CONSTRAINT_MGR       OTHER                      Import logic is not creatingmodel-defined differential pairs.